Serial memory devises typically have a single input clock pin and a single input/output (I/O) pin for providing data. Although there are many product specific and proprietary protocols, for accessing such devices, many industry standards are known and in the public domain.
Communications of data and clock information frequently occurs via a single-wire form of transfer. Such communications are often used in memory chip transfers (e.g., between flash memory, EEPROMs, etc.). Some prior art schemes use a pulse width of the data to define the protocol. For example, the duration of a “1” data pulse is longer than a duration of a “0” data pulse. FIG. 1A shows an ideal output utilizing a pulse width modulation protocol. A first pulse 101 is indicative of a “0” (or logic low) transmission while a second pulse 103 is indicative of a “1” (or logic high) transmission.
A problem with this pulse width protocol is that noise can affect it in such a way that it becomes difficult to determine the duration of the data pulse. Consequently, errors occur in reading the data pulses. FIG. 1B shows an example of a typical prior art transmission signal with noise. A first pulse 105 is indicative of a “0” transmission. However, a second pulse train 107 and a third pulse train 109 cannot be clearly discerned due to excessive noise. Indeed, the second and third pulse trains 107 and 109 each contain a plurality of data pulses, although an exact number of pulses is unknown.
Error detection and correction circuits are generally used with protocols of this type to alleviate the inaccuracies in reading the data. However, these error detection/correction circuits take up valuable real estate on an integrated circuit chip. Therefore, it is not desirable to use pulse width modulation protocols and rely on error correction techniques to accurately transmit clock and data over a single wire.
What is needed is a high, speed read access in a serial, single wire transmission which can be achieved without excessive circuitry and/or cost. It is a further desire to provide such capability without excessive power requirements.